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74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
March 2007
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Features
Edge-triggered D-type inputs Buffered positive edge-triggered clock 3-STATE outputs for bus-oriented applications Output sink capability of 64mA, source capability of
tm
General Description
The ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
32mA Guaranteed output skew Guaranteed multiple output switching specifications Output switching specified for both 50pF and 250pF loads Guaranteed simultaneous switching, noise level and dynamic threshold performance Guaranteed latchup protection High-impedance, glitch-free bus loading during entire power up and power down cycle Nondestructive, hot-insertion capability
Ordering Information
Order Number
74ABT374CSC 74ABT374CSCX_NL(1) 74ABT374CSJ 74ABT374CMSA 74ABT374CMTC
Package Number
M20B M20B M20D MSA20 MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number. Pb-Free package per JEDEC J-STD-020B. Note: 1. Device available in Tape and Reel only.
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Connection Diagram
Pin Descriptions
Pin Names
D0-D7 CP OE O0-O7 Data Inputs Clock Pulse Input (Active Rising Edge) 3-STATE Output Enable Input (Active LOW) 3-STATE Outputs
Description
Functional Description
The ABT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Function Table
Inputs OE CP D
H H H H L L L L H H H H L H L H L H L H
Internal Outputs Q
NC NC L H L H NC NC
O
Z Z Z Z L H NC NC
Function
Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4 www.fairchildsemi.com 2
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
TSTG TA TJ VCC VIN IIN VO Storage Temperature
Parameter
Ambient Temperature Under Bias Junction Temperature Under Bias VCC Pin Potential to Ground Pin Input Voltage(2) Input Current(2) Voltage Applied to Any Output Disabled or Power-Off State HIGH State Current Applied to Output in LOW State (Max.) DC Latchup Source Current Across Common Operating Range OE Pin Other Pins Over Voltage Latchup (I/O)
Rating
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30mA to +5.0mA -0.5V to 5.5V -0.5V to VCC twice the rated IOL (mA) -150mA -500mA 10V
Note: 2. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
TA VCC V / t Supply Voltage Minimum Input Edge Rate Data Input Enable Input Clock Input
Parameter
Free Air Ambient Temperature
Rating
-40C to +85C +4.5V to +5.5V 50mV/ns 20mV/ns 100mV/ns
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 3
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
DC Electrical Characteristics
Symbol
VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT
Parameter
Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE
VCC
Conditions
Recognized HIGH Signal Recognized LOW Signal
Min.
2.0
Typ.
Max. Units
V 0.8 -1.2 V V V 0.55 1 1 7 -1 -1 A A V 10 -10 A A mA A A A mA A mA mA mA mA/ MHz V A
Min. Min. Min. Max. Max. Max. 0.0
IIN = -18mA IOH = -3mA IOH = -32mA IOL = 64mA VIN = 2.7V VIN = VCC VIN = 7.0V VIN = 0.5V(4) VIN = 0.0V IID = 1.9A, All Other Pins Grounded 4.75
(4)
2.5 2.0
0-5.5V VOUT = 2.7V, OE = 2.0V 0-5.5V VOUT = 0.5V, OE = 2.0V Max. Max. 0.0 Max. Max. Max. Max. VOUT = 0.0V VOUT = VCC VOUT = 5.5V, All Others VCC or GND All Outputs HIGH All Outputs LOW OE = VCC, All Others at VCC or GND VI = VCC - 2.1V Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V, All Others at VCC or GND Max. Outputs OPEN, OE = GND(3), One-Bit Toggling, 50% Duty Cycle -100
-275 50 100 50 30 50 2.5 2.5 2.5 0.30
ICCD
Dynamic ICC No Load(4)
Notes: 3. For 8-bit toggling, ICCD < 0.8mA/MHz. 4. Guaranteed, but not tested.
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 4
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
DC Electrical Characteristics
SOIC package.
Symbol
VOLP VOLV VOHV VIHD VILD
Parameter
Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage
VCC
5.0 5.0 5.0 5.0 5.0
Conditions CL = 50pF, RL = 500
TA = TA = TA = 25C(5) 25C(5) 25C(6)
Min.
-1.3 2.5 2.0
Typ.
0.5 -0.9 3.0 1.6 1.3
Max. Units
0.8 V V V V 0.8 V
TA = 25C(7) TA = 25C(7)
Notes: 5. Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. 6. Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. 7. Max number of data inputs (n) switching. n - 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested.
AC Electrical Characteristics
SOIC and SSOP package.
TA = +25C, VCC = +5V, CL = 50pF Symbol
fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time
TA = -55C to +125C, TA = -40C to +85C, VCC = 4.5V to 5.5V, VCC = 4.5V to 5.5V, CL = 50pF CL = 50pF Min.
150
Parameter
Maximum Clock Frequency Propagation Delay CP to On Output Enable Time
Min.
150 2.0 2.0 1.5 1.5 1.5 1.5
Typ.
200 3.2 3.3 3.1 3.1 3.6 3.4
Max.
Max.
Min.
150
Max.
Units
MHz
5.0 5.0 5.3 5.3 5.4 5.4
1.4 2.0 0.8 1.5 1.3 1.0
6.6 7.6 5.7 7.2 7.2 7.0
2.0 2.0 1.5 1.5 1.5 1.5
5.0 5.0 5.3 5.3 5.4 5.4
ns ns ns
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 5
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
AC Operating Requirements
TA = +25C VCC = +5.0V CL = 50pF Symbol
tS(H) tS(L) tH(H) tH(L) tW(H) tW(L)
TA = -55C to +125C TA = -40C to +85C VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V CL = 50pF CL = 50pF Min.
2.5 2.5 2.5 2.5 3.3 3.3
Parameter
Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Pulse Width, CP HIGH or LOW
Min.
1.5 1.5 1.0 1.0 3.0 3.0
Max.
Max.
Min.
1.0 1.5 1.0 1.0 3.0 3.0
Max.
Units
ns ns ns
Extended AC Electrical Characteristics
SOIC package.
TA = -40C to +85C, TA = -40C to +85C, VCC = 4.5V to 5.5V, VCC = 4.5V to 5.5V, CL = 50pF, TA = -40C to +85C, CL = 250pF, 8 Outputs VCC = 4.5V to 5.5V, 8 Outputs Switching(8) CL = 250pF(9) Switching(10) Symbol
tPLH tPHL tPZH tPZL tPHZ tPZL
Parameter
Propagation Delay CP to On Output Enable Time Output Disable Time
Min
1.5 1.5 1.5 1.5 1.0 1.0
Max
5.7 5.7 6.2 6.2 5.5 5.5
Min
2.0 2.0 2.0 2.0
(11)
Max
7.8 7.8 8.0 8.0
Min
2.0 2.0 2.0 2.0
(11)
Max
10.0 10.0 10.5 10.5
Units
ns ns ns
Notes: 8. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). 9. This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. This specification pertains to single output switching only. 10. This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 11. The 3-STATE delay Time is dominated by the RC network (500, 250pF) on the output and has been excluded from the datasheet.
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 6
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Skew(16)
SOIC package.
TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF 8 Outputs Switching(12) Symbol
tOSHL
(14)
TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 8 Outputs Switching(13) Max.
1.8 1.8 4.3 4.3 4.6
Parameter
Pin to Pin Skew, HL Transitions Pin to Pin Skew, LH Transitions Duty Cycle, LH-HL Skew Pin to Pin Skew, LH/HL Transitions Device to Device Skew, LH/HL Transitions
Max.
1.0 1.0 1.8 2.0 2.5
Units
ns ns ns ns ns
tOSLH(14) tPS(13) tOST
(14)
tPV(15)
Notes: 12. This specification is guaranteed but not tested. The limits represent propagation delays with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 13. This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. 14. Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST). This specification is guaranteed but not tested. 15. Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. 16. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Capacitance
Symbol
CIN COUT
(17)
Parameter
Input Capacitance Output Capacitance VCC = 0V
Conditions TA = 25C
VCC = 5.0V
Typ.
5.0 9.0
Units
pF pF
Note: 17. COUT is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012.
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 7
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
AC Loading
*Includes jig and probe capacitance Figure 1. Standard AC Test Load Input Pulse Requirements Figure 2. VM = 1.5V
Amplitude
3.0V
Rep. Rate
1 MHz
tw
500ns
tr
2.5ns
tf
2.5ns
Figure 3. Test Input Signal Requirements
AC Waveforms
Figure 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
Figure 6. 3-STATE Output HIGH and LOW Enable and Disable Times
Figure 5. Propagation Delay, Pulse Width Waveforms Figure 7. Setup Time, Hold Time and Recovery Time Waveforms
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 8
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 9
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted.
Figure 9. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 10
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted.
Figure 10. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 11
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted.
Figure 11. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 12
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
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DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only.
Rev. I24
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
No Identification Needed
Full Production
Obsolete
Not In Production
(c)1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4
www.fairchildsemi.com 13

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